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ECE352_28Slide 1 Lecture 28 Computer Design BasicsLecture 28 Computer Design Basics
Slide 2 OverviewOverview Datapaths ALU Shifter Datapath representation Datapath operations Control word Simple Computer Architecture Instruction Set Architecture (ISA) Instruction Formats Single-Cycle Hardwired Control
Slide 3 Designing Computers 101Designing Computers 101 We describe a computer s appearance (as seen by a programmer) at the lowest level as an instruction set architecture (ISA). The instructions and operands a machine can use are the basis of the ISA. At a basic level, the computer architecture is divided into datapath and control. This datapath is defined by a set of registers, the possible microoperations, and the control interface.
Slide 4 The Basic DatapathThe Basic Datapath A basic datapath will consist of two major components; The register file, which contains the register set and the logic required to be able to supply operands for operations and to store the results of operations in the destination register(s). The function unit, which performs the actual transformations required to complete microoperations.
Slide 5 DatapathDatapath Two major components: The register file The function unit
Slide 6 The ALUThe ALU Instead of dedicated logic per register, computers have a shared logic unit This is the arithmetic logic unit, or ALU. The ALU is a combinational circuit that performs; Arithmetic (add/subtract/complement) Logical operations (AND/OR/XOR/NOT) The ALU may or may not perform shifts.
Slide 7 Shifter DesignShifter Design Shift registers Parallel load, shift left or right, read out value Separate register from shift logic and place shift logic in ALU Use multiplexers to implement 4-bit shift logic capable of arithmetic and logical, left and right shifts
Slide 8 Datapath RepresentationDatapath Representation Datapath contains: Register file Function unit Additional logic and connections for system interaction (i.e. memory read/write, external constants, etc.)
Slide 9 Datapath OperationDatapath Operation The datapath completes a single microoperation each clock cycle. For given microoperation, we need to specify; Source registers Destination register Operation to perform For the datapath, we also need to specify; External or function data Data B from register or constant Whether the destination is updated
Slide 10 Control WordControl Word The required information to specify a datapath operation is encoded in a control word. A uniform format that covers all operations is desirable note that some information is not needed for all operations.
Slide 11 The Control Word FieldsThe Control Word Fields Fields DA D Address AA A Address BA B Address MB Mux B FS Function Select MD Mux D RW Register Write Control word D A AA BA M B FS M D R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Slide 12 Stored Program ComputerStored Program Computer Control words operate the datapath Store control words in memory Sequence through them to perform a series of computational steps This is what a computer does
Slide 13 Simple Computer ArchitectureSimple Computer Architecture A computer is controlled by a series of instructions. Instructions are binary words that are used to determine both the datapath processing and the control behavior. A program is a collection of instructions that are used to accomplish some task(s). A program counter (PC) is used to keep track of the address of the next instruction in memory. The PC has counting logic, as well as parallel load and other logic to permit changes in the instruction sequence.
Slide 14 Simple Computer ArchitectureSimple Computer Architecture Changes in the instruction sequence can be either conditional or unconditional. Instructions are executed by activating the necessary microoperations to perform the specified task. Note that the computer uses programmable control, but we will use a hardwired control unit to actually implement the programmable control.
Slide 15 Instruction Set Architecture (ISA)Instruction Set Architecture (ISA) The instruction set architecture (ISA) a comprehensive description of the instructions a computer can execute. The ISA has three major components Storage Resources Instruction Formats Instruction Specification
Slide 16 Storage ResourcesStorage Resources From the programmer s viewpoint, the computer has various resources available for storing information Register file Program counter (PC) Instruction memory (program memory) Data memory Data and program memory may be distinct, or they may exist in the same memory.
Slide 17 Instruction FormatsInstruction Formats Instructions are divided into bit groupings called fields. Each field will contain a specific part of the instruction. Operation code (opcode) An n-bit opcode can specify up to 2n different operations. Operand(s) Registers Addresses Constant data Operands may be specified implicitly as well.
Slide 18 Instruction FormatsInstruction Formats The source(s) and destination of an instruction can all be registers. The opcode field determines what the actual register transfer operation will be. The source registers are read and the new information is written to the destination register. All registers are explicitly identified (usually).
Slide 19 Instruction FormatsInstruction Formats Immediate operands are data constants contained within the instruction. Note that only three bits of data can be specified here, so it must be extended to the register length by zero-fill or sign-extension. Clever encodings enable wider immediates RR format, RI format, B format
Slide 20 Instruction FormatsInstruction Formats Changes in program flow are caused by jump or branch instructions, affecting only the PC. Can load the PC from source register A. Can add the sign-extended 6-bit offset (AD) to the PC. Can be either unconditional, or conditional based on some flag value (i.e. Z, N, C, V).
Slide 21 Instruction SpecificationsInstruction Specifications The instruction specifications describe in detail each instruction the system can execute. A mnemonic is by the programmer to represent the opcode in text, an assembler then generates the actual binary instruction. Not every instruction sets every flag Refer to Table 10-8 on p. 454
Slide 22 Single-Cycle Hardwired ControlSingle-Cycle Hardwired Control In single-cycle hardwired control, the PC is updated on each clock cycle. Each instruction is completed in a single cycle. The PC is used to select a word from the instruction memory, which is driven to the instruction decoder. The instruction decoder then provides the control word to the datapath to activate the desired functionality, and determines how the PC is updated.
Slide 23 Control UnitControl Unit The constant field is zero-filled and made available to the datapath The concatenated offset field is sign-extended for PC-relative addressing. PL if 0, the PC increments, otherwise the update is controlled by JB JB if 0, do conditional branch, otherwise do unconditional jump BC if 0, do BRZ, otherwise do BRN MW if 1, will write to external memory The instruction decoder maps the instruction word to a control word. Good design practice is to minimize the complexity of this operation.
Slide 24 Single-Cycle Computer IssuesSingle-Cycle Computer Issues Complex operations Only combinational logic can be used in data transformation no sequential logic E.g. no multiplier Unified memory If program and data are in one memory, how can you simultaneously access the same memory for an instruction and a data operand? Worst-case delay
Slide 25 SummarySummary Datapaths ALU Shifter Datapath representation Datapath operations Control word Simple Computer Architecture Instruction Set Architecture (ISA) Storage, Instruction Formats & Specifications Single-Cycle Hardwired Control
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