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Chapter 2 - Part 1 - PPT - Mano & Kime - 2nd EdSlide 1 Lecture 27 Memory BasicsLecture 27 Memory Basics
Slide 2 OverviewOverview Memory definitions Random Access Memory (RAM) Static RAM (SRAM) integrated circuits Cells and slices Cell arrays and coincident selection Arrays of SRAM integrated circuits Dynamic RAM (DRAM) integrated circuits DRAM Types Synchronous (SDRAM) Double-Data Rate (DDR SRAM) Arrays of DRAM integrated circuits
Slide 3 Memory DefinitionsMemory Definitions Memory Storage cells and circuits to transfer information to and from them Memory Organization structure that determines how data is accessed Random Access Memory (RAM) uniform access latency to any element in the memory Memory Address A vector of bits that identifies a particular memory element
Slide 4 Memory Definitions (Continued)Memory Definitions (Continued) Typical data elements are: bit a single binary digit byte a collection of eight bits accessed together word a collection of binary bits whose size is a typical unit of access for the memory. It is typically a power of two multiple of bytes (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.) Memory Data a bit or a collection of bits to be stored into or accessed from memory cells. Memory Operations Typically, read and write operations over some data element (bit, byte, word, etc.).
Slide 5 Memory Block DiagramMemory Block Diagram A basic memory system is shown here: k address lines are decoded to address 2k words of memory. Each word is n bits. Read and Write control lines enable reading from and writing to memory n Data Input Lines k Address Lines Read Write n Data Output Lines Memory Unit 2k Words n Bits per Word k 1 1 n n
Slide 6 Memory Organization ExampleMemory Organization Example Example memory contents: A memory with 3 address bits & 8 data bits has: k = 3 and n = 8 so 23 = 8 addresses labeled 0 to 7. 23 = 8 words of 8-bit data Memory Address Binary Decimal Memory Content 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 2 1 0 1 1 0 0 0 1 0 1 1 3 0 0 0 0 0 0 0 0 1 0 0 4 1 0 1 1 1 0 0 1 1 0 1 5 1 0 0 0 0 1 1 0 1 1 0 6 0 0 1 1 0 0 1 1 1 1 1 7 1 1 0 0 1 1 0 0
Slide 7 Basic Memory OperationsBasic Memory Operations Memory operations 3-tuple: Data written to or read from memory Address specifies memory location Command READ or WRITE
Slide 8 Basic Memory Operations (continued)Basic Memory Operations (continued) Read Memory Place a valid address on the address lines. Wait for the read data to become stable. Write Memory Place a valid address on the address lines and valid data on the data lines. Toggle the memory write control line Usually the write enable line is defined as a clock with precise timing requirements (e.g. Write Strobe). Otherwise, it is just an interface signal. Sometimes memory must acknowledge that it has completed the operation.
Slide 9 Memory Operation TimingMemory Operation Timing Most basic memories are asynchronous Storage in latches or storage of electrical charge No clock Controlled by control inputs and address Timing of signal changes and data observation is critical to the operation Read timing: Read cycle Clock Address Memory enable Read/ Write Data output 20 ns T1 T2 T3 T4 T1 Address valid 65 ns Data valid
Slide 10 Memory Operation TimingMemory Operation Timing Write timing: Critical times measured with respect to edges of write pulse (1-0-1): Setup and hold time for address: address must be valid before pulse begins and held beyond end of pulse to avoid disturbing stored contents of other addresses Setup and hold for data: data must be valid before end of pulse and held beyond end of pulse to write correctly Write cycle Clock Address Memory enable Read/ Write Data input 20 ns T1 T2 T3 T4 T1 Address valid Data valid 75 ns
Slide 11 RAM Integrated CircuitsRAM Integrated Circuits Types of random access memory Static information stored in latches Dynamic information stored as electrical charges on capacitors Charge leaks off Periodic refresh of charge required Dependence on Power Supply Volatile loses stored information when power turned off Non-volatile retains information when power turned off
Slide 12 Static RAM CellStatic RAM Cell Array of storage cells used to implement static RAM Storage Cell SR Latch Select input for control Dual Rail Data Inputs B and B Dual Rail Data Outputs C and C Select B RAM cell C C B S R Q Q
Slide 13 Static RAM Bit SliceStatic RAM Bit Slice Represents all circuitry that is required for 2n 1-bit words Multiple RAM cells Control Lines: Word select i one for each word Bit Select Data Lines: Data in Data out (a) Logic diagram Select S R Q Q B RAM cell C C B Select S R Q Q RAM cell X Word select 0 Word select 2 n 1 Data in Write logic Read/ Write Bit select S R Q Q X X X Word select 0 Word select 1 Word select 2 n Read/Write logic Data in Data out Read/ Write Bit select (b) Symbol RAM cell RAM cell RAM cell Data out Read logic 1
Slide 14 2n-Word 1-Bit RAM ICRead/ 2n-Word 1-Bit RAM IC To build a RAM IC from a RAM slice, we need: Decoder decodes the n address lines to 2n word select lines A 3-state buffer on the data output permits RAM ICs to be combined into a RAM with c 2n words Word select Read/Write logic Data in Data out Write Bit select (b) Block diagram RAM cell RAM cel l RAM cell Data input Chip select Read/Write Data output A 3 A 2 A 1 A 0 2 3 2 2 2 1 2 0 4-to-16 Decoder 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 3 A 2 A 1 A 0 Data input Data output (a) Symbol Read/ Write Memory enable 16 x 1 RAM
Slide 15 Cell Arrays and Coincident SelectionMemory arrays can be very large => Large decoders Large fanouts for the bit lines The decoder size and fanouts can be reduced by approximately by using a coincident selection in a 2-dimensional array Uses two decoders, one for words and one for bits Word select becomes Row select Bit select becomes Column select See next slide for example A3 and A2 used for Row select A1 and A0 for Column select Cell Arrays and Coincident Selection
Slide 16 Cell Arrays and Coincident Selection (continued)Cell Arrays and Coincident Selection (continued) Data input Read/Write X X X A 1 A 0 RAM cell 0 RAM cell 4 RAM cell 8 RAM cell 12 Read/Write logic Data in Data out Read/ Write Bit select RAM cell 1 RAM cell 5 RAM cell 9 RAM cell 13 Read/Write logic Data in Data out Read/ Write Bit select RAM cell 2 RAM cell 6 RAM cell 10 RAM cell 14 Read/Write logic Data in Data out Read/ Write Bit select RAM cell 3 RAM cell 7 RAM cell 11 RAM cell 15 Read/Write logic Data in Data out Read/ Write Bit select Column decoder 2-to-4 Decoder with enable 2 1 2 0 0 1 Column select 2 Enable 3 Chip select Data output Row select Row decoder A 2 A 3 X 2-to-4 Decoder 2 0 2 1 1 2 3 0
Slide 17 RAM ICs with 1 Bit/WordRAM ICs with > 1 Bit/Word Word length can be quite high. To better balance the number of words and word length, use ICs with > 1 bit/word
Slide 18 RAM with 2 Bits/WordRAM with 2 Bits/Word Figure 9-8 2 input bits 2 output bits Row select chooses 4 cells Column select chooses within pairs of columns
Slide 19 Making Larger MemoriesMaking Larger Memories Tie all address, data, and R/W lines in parallel Decode high-order address bits to control CS Use 4x1 memories to construct 16x1 memory
Slide 20 Making Wider MemoriesMaking Wider Memories Tie address and control lines in parallel Keep the data lines separate Make a 4x4 memory from 4x1 memories
Slide 21 Dynamic RAM (DRAM)Dynamic RAM (DRAM) Basic Principle: Storage of information on capacitors. Charge and discharge of capacitor to change stored value Use of transistor as switch to: Store charge Charge or discharge
Slide 22 Dynamic RAM (continued)Dynamic RAM (continued) (a) (c) Select D C Q B DRAM cell model C (f) (g) (h) Select B T C DRAM cell To Pump (b) (d) (e) Stored 1 Stored 0 Write 1 Write 0 Read 1 Read 0
Warning: (d), (e), (f), and (g) are animated. Each animation is triggered with a mouse click and goes through two steps at 1 second intervals.
Slide 23 Dynamic RAM - Bit SliceDynamic RAM - Bit Slice C is driven by 3-state drivers Sense amplifier is used to change the small voltage change on C into H or L Data in (b) Symbol (a) Logic diagram Select B Select Word select 0 Word select 2 n 2 1 Write logic Bit select Data out Read logic D C Q DRAM cell model D C Q DRAM cell model C Sense amplifier Read/Write logic Data in Data out Bit select DRAM cell DRAM cell DRAM cell Word select 0 Word select 1 Word select 2 n 2 1 Read/ Write Read/ Write
Slide 24 Dynamic RAM - Block DiagramDynamic RAM - Block Diagram
The address is split to roughly halve the large number of address pins on the typical RAM IC. The row address is used to select the row of cells to be read within the memory. The column address is used to select the word to be placed on the output from the data read from the row of cells. Since the data must be read from the cells before it can be selected, the row address must be applied first.
Slide 25 Dynamic RAM Read TimingDynamic RAM Read Timing Read cycle 20 ns T1 T2 T3 T4 T1 Data valid 65 ns Hi-Z Read/ Write Data output Clock Row Address Column Address RAS CAS Address Output enable
Slide 26 Synchronous DRAM w/Burst ReadSynchronous DRAM w/Burst Read Transfers to and from the DRAM are synchronized with a clock Synchronous registers appear on: Address input Data input Data output Column address counter for addressing internal data to be transferred on each clock cycle beginning with the column address counts up to column address + burst size 1 Example: Memory data path width: 1 word = 4 bytes Burst size: 8 words = 32 bytes Memory clock period: 5 ns (200 MHZ) Latency to first word: 4 clock cycles Read cycle time: (4 + 8) x 5 ns = 60 ns Memory Bandwidth: 32/(60 x 10-9) = 533 Mbytes/sec
Slide 27 Double Data Rate Synchronous DRAMDouble Data Rate Synchronous DRAM Transfers data on both edges of the clock Provides a transfer rate of 2 data words per clock cycle Example: Same as for synchronous DRAM Read cycle time = 60 ns Memory Bandwidth: (2 x 32)/(60 x 10-9) = 1.066 Mbytes/sec
Slide 28 Arrays of DRAM Integrated CircuitsArrays of DRAM Integrated Circuits Similar to arrays of SRAM ICs, but there are differences typically handled by an IC called a DRAM controller: Separation of the address into row address and column address and timing their application Providing RAS and CAS and timing their application Performing refresh operations at required intervals Providing status signals to the rest of the system (e.g., indicating whether or not the memory is active or is busy performing refresh)
Slide 29 SummarySummary Memory definitions Random Access Memory (RAM) Static RAM (SRAM) integrated circuits Cells and slices Cell arrays and coincident selection Arrays of SRAM integrated circuits Dynamic RAM (DRAM) integrated circuits DRAM Types Synchronous (SDRAM) Double-Data Rate (DDR SRAM) Arrays of DRAM integrated circuits
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