eTEACH presentation accessible player instructionseTEACH presentation accessible player instructionsThis eTEACH player requires that you have Flash 8 or above installed. If you do not, download the player from Adobe.
The next major heading marks the start of the presentation. Each next lower level heading thereafter marks the beginning of a slide. An audio control button that plays the audio track for the slide follows the contents and notes for each slide in the presentation. Pressing this button after the audio playback toggles pausing and resuming the playback. Before moving off the play audio button, complete listening to the audio track for the slide or pause the audio. Control + Shift + L increases volume. Control + Shift + Q decreases volume.
There is a table of contents for the presentation following the presentation. The table of contents can be used to access sections of the presentation in random order. Type Control + Shift + C to go to the table of contents.
When links to external resources are present in the presentation, a list of these resource links follows the table of contents. When following a link to a resource, you should remember which slide you were on. When you return to the main page, your screen-reader may not return you to that slide. You can use the table of contents or just click through the headings to return to the correct slide.
This presentation contains resources. Click here to proceed immediately to the resource list. A link to resources follows each slide.
If the presentation contains one or more quizzes, a button to take you to each quiz follows the slide at which the quiz is to occur. Each question in the quiz begins with a level three heading. The answer choices will be presented in a list. If your instructor has supplied a hint for the questions, it will follow the answers and is formatted as an anchor. The correct answer to the question follows the list of answers and the hint (if included). The correct answer is also formatted as an anchor.
Chapter 2 - Part 1 - PPT - Mano & Kime - 2nd EdSlide 1 Lecture 24 Counters, Register Cells, Buses, and Serial OperationsLecture 24 Counters, Register Cells, Buses, and Serial Operations
Slide 2 OverviewOverview Microoperations on single register Counters Register cell design Multiplexer and bus-based transfers for multiple registers Serial transfers and microoperations
Slide 3 CountersCounters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage: Ripple Counters Inexpensive, easy to implement Asynchronous (output used as clock) Synchronous Counters Clock is directly connected to the flip-flop clock inputs Logic is used to implement the desired state sequencing Counters
Slide 4 Ripple CounterHow does it work? When there is a positive edge on the clock input of A, A complements The clock input for flip- flop B is the complemented output of flip-flop A When flip A changes from 1 to 0, there is a positive edge on the clock input of B causing B to complement Reset Clock D D CR CR B A Ripple Counter CP B A 0 1 2 3 0 1
Slide 5 Ripple Counter (continued)The arrows show the cause-effect relation- ship from the prior slide => The corresponding sequence of states => (B,A) = (0,0), Each additional bit, C, D, …behaves like bit B, changing half as frequently as the bit before it. For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), … Ripple Counter (continued) (1,0), (0,1), (0,1), … (0,0), (1,1), CP B A 0 1 2 3 0 1
Slide 6 Ripple Counter (continued)These circuits are called ripple counters because each edge sensitive transition (positive in the example) causes a change in the next flip-flop s state. The changes ripple upward through the chain of flip-flops, i. e., each transition occurs after a clock-to-output delay from the stage before. To see this effect in detail look at the waveforms on the next slide. Ripple Counter (continued)
Slide 7 Ripple Counter (continued)Starting with C = B = A = 1, equivalent to (C,B,A) = 7 base 10, the next clock increments the count to (C,B,A) = 0 base 10. In fine timing detail: The clock to output delay tPHL causes an increasing delay from clock edge for each stage transition. Thus, the count ripples from least to most significant bit. For n bits, total worst case delay is n tPHL. Ripple Counter (continued) CP A B C tPHL tPHL tpHL
Slide 8 Synchronous CountersSynchronous Counters To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer => D3 Q3 D2 Q2 D1 Q1 D0 Q0 Clock Incre-menter A3 A2 A1 A0 S3 S2 S1 S0
Slide 9 Synchronous Counters (continued)Internal details => Internal Logic XOR complements each bit AND chain causes complement of a bit if all bits toward LSB from it equal 1 Count Enable Forces all outputs of AND chain to 0 to hold the state Carry Out Added as part of incrementer Connect to Count Enable of additional 4-bit counters to form larger counters Synchronous Counters (continued) Incrementer Adobe Systems
Slide 10 Synchronous Counters (continued)Carry chain series of AND gates through which the carry ripples Yields long path delays Called serial gating Replace AND carry chain with ANDs => in parallel Reduces path delays Called parallel gating Like carry lookahead Lookahead can be used on COs and ENs to prevent long paths in large counters Symbol for Synchronous Counter Synchronous Counters (continued) Adobe Systems
Slide 11 Counter with Parallel LoadAdd path for input data enabled for Load = 1 Add logic to: disable count logic for Load = 1 disable feedback from outputs for Load = 1 enable count logic for Load = 0 and Count = 1 The resulting function table: D 0 D C Q 0 D 1 D C Q 1 D 2 D C Q 2 D 3 D C Q 3 Load Count Clock Carry Output CO Counter with Parallel Load
Slide 12 Other CountersOther Counters See text for: Down Counter - counts downward instead of upward Up-Down Counter - counts up or down depending on value a control input such as Up/Down Parallel Load Counter - Has parallel load of values available depending on control input such as Load Divide-by-n (Modulo n) Counter Count is remainder of division by n where n may not be a power of 2 or Count is arbitrary sequence of n states specifically designed state-by-state Includes modulo 10 which is the BCD counter
Slide 13 Counting Modulo NThe following techniques use an n-bit binary counter with asynchronous or synchronous clear and/or parallel load: Detect a terminal count of N in a Modulo-N count sequence to asynchronously Clear the count to 0 or asynchronously Load in value 0 (These lead to counts which are present for only a very short time and can fail to work for some timing conditions!) Detect a terminal count of N - 1 in a Modulo-N count sequence to Clear the count synchronously to 0 Detect a terminal count of N - 1 in a Modulo-N count sequence to synchronously Load in value 0 Detect a terminal count and use Load to preset a count of the terminal count value minus (N - 1) Alternatively, custom design a modulo N counter Counting Modulo N
Slide 14 Counting Modulo 7: Detect 7 and Asynchronously ClearA synchronous 4-bit binary counter with an asynchronous Clear is used to make a Modulo 7 counter. Use the Clear feature to detect the count 7 and clear the count to 0. This gives a count of 0, 1, 2, 3, 4, 5, 6, 7(short)0, 1, 2, 3, 4, 5, 6, 7(short)0, etc. DON T DO THIS! Referred to as a suicide counter! (Count 7 is killed, but the designer s job may be dead as well!) Counting Modulo 7: Detect 7 and Asynchronously Clear Clock 0 D3 Q3 D2 Q2 D1 Q1 D0 Q0 CLEAR CP LOAD
Slide 15 Counting Modulo 7: Synchronously Load on Terminal Count of 6A synchronous 4-bit binary counter with a synchronous load and an asynchronous clear is used to make a Modulo 7 counter Use the Load feature to detect the count "6" and load in "zero". This gives a count of 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 0, ... Using don t cares for states above 0110, detection of 6 can be done with Load = Q2 Q1 Counting Modulo 7: Synchronously Load on Terminal Count of 6 D3 Q3 D2 Q2 D1 Q1 D0 Q0 CLEAR CP LOAD Clock 0 0 0 0 Reset
Slide 16 Register Cell DesignRegister Cell Design Assume that a register consists of identical cells Then register design can be approached as follows: Design representative cell for the register Connect copies of the cell together to form the register Applying appropriate boundary conditions to cells that need to be different and contract if appropriate Register cell design is the first step of the above process
Slide 17 Register Cell SpecificationsA register Data inputs to the register Control input combinations to the register Example 1: Not encoded Control inputs: Load, Shift, Add At most, one of Load, Shift, Add is 1 for any clock cycle (0,0,0), (1,0,0), (0,1,0), (0,0,1) Example 2: Encoded Control inputs: S1, S0 All possible binary combinations on S1, S0 (0,0), (0,1), (1,0), (1,1) Register Cell Specifications
Slide 18 Register Cell SpecificationsA set of register functions (typically specified as register transfers) Example: Load: A ← B Shift: A ← sr B Add: A ← A + B A hold state specification Example: Control inputs: Load, Shift, Add If all control inputs are 0, hold the current register state Register Cell Specifications
Slide 19 Multiplexer ApproachMultiplexer Approach Uses an n-input multiplexer with a variety of transfer sources and functions Adobe Systems
Slide 20 Multiplexer ApproachMultiplexer Approach Load enable by OR of control signals K0, K1, … Kn-1 - assumes no load for 00…0 Use: Encoder + Multiplexer (shown) or n x 2 AND-OR to select sources and/or transfer functions Adobe Systems
Slide 21 Example 1: Register Cell DesignRegister A (m-bits) Specification: Data input: B Control inputs (CX, CY) Control input combinations (0,0), (0,1) (1,0) Register transfers: CX: A ← B v A CY :A ← B + A Hold state: (0,0) Example 1: Register Cell Design
Slide 22 Example 1: Register Cell Design (continued)Load Control Load = CX + CY Since all control combinations appear as if encoded (0,0), (0,1), (1,0) can use multiplexer without encoder: S1 = CX S0 = CY D0 = Ai Hold A D1 = Ai ← Bi + Ai CY = 1 D2 = Ai ← Bi v Ai CX = 1 Note that the decoder part of the 3-input multiplexer can be shared between bits if desired Example 1: Register Cell Design (continued)
Slide 23 Sequential Circuit Design ApproachSequential Circuit Design Approach Procedure Find a state diagram or state table Use the design procedure in Chapter 6 to complete the cell design Optimize (K-map, automated tools) Will likely result in less expensive design Less reusable or general-purpose
Slide 24 Example 1 AgainState Table: Four variables give a total of 16 state table entries By using: Combinations of variable names and values Don t care conditions (for CX = CY = 1) only 8 entries are required to represent the 16 entries Example 1 Again
Slide 25 Example 1 Again (continued)The resulting SOP equation: Di = CX Bi + CY Ai Bi + Ai Bi + CY Ai Using factoring and DeMorgan s law: Di = CX Bi + Ai (CY Bi) + Ai(CY Bi ) Di = CX Bi + Ai + (CY Bi) The gate input cost per cell = 2 + 8 + 2 + 2 = 14 The gate input cost per cell for the mux-based design was: Per cell: 19 Shared decoder logic: 8 Cost gain by sequential design > 5 per cell Also, no Enable on the flip-flop makes it cheaper Example 1 Again (continued)
Slide 26 Multiplexer and Bus-Based Transfers for Multiple RegistersMultiplexer and Bus-Based Transfers for Multiple Registers Multiplexer dedicated to each register Shared transfer paths for registers A shared transfer object is a called a bus (Plural: buses) Bus implementation using: multiplexers three-state nodes and drivers In most cases, the number of bits is the length of the receiving register
Slide 27 Dedicated MUX-Based TransfersDedicated MUX-Based Transfers Multiplexer connected to each register input produces a very flexible transfer structure => Simultaneous transfers: Any to any Up to three per cycle Totally flexible S0 S1 S2 L0 L1 L2 n n MUX S 0 1 n R0 Load n n MUX S 0 1 n R1 Load n n MUX S 0 1 n R2 Load
There can be three distinct registers as source, so can simultaneously do any three register transfers - totally flexible.
Slide 28 Multiplexer BusMultiplexer Bus A single bus driven by a multiplexer lowers cost, but limits the available transfers => Simultaneous transfers One source per cycle Much lower in cost Wires/gates L0 n n MUX S1 S0 0 1 n 2 S0 S1 L1 L2 n R0 Load n R1 Load n R2 Load n
Can have only one register as a source at a time. Thus a set of simultaneous transfers can have only one register source. Could require up to three clock cycles if three different sources needed. Costs: Dedicated 18 gate inputs per bit plus 3 shared inverters with total of 3 inputs Bus: 9 gate inputs per bit + shared decoder with 8 inputs Bus clearly less costly.
Slide 29 Three-State BusThree-State Bus The 3-input MUX can be replaced by a 3-state node (bus) and 3-state buffers. Cost is further reduced, but transfers are limited Least costly Just a mux implemented with 3-state buffers n L0 L1 L2 n R0 Load n R1 Load n R2 Load n n E2 E1 E0
Same simultaneous transfer capability as multiplexer bus Cost: 3 gate inputs per three state driver = 9 gate inputs If decoder desired, 8 shared gate inputs. Clearly least costly. The bus is unique in that it is bidirectional. This is a significant advantage since it cuts connections between chips for bus paths to 1/2.
Slide 30 Serial Transfers and MicrooperationsSerial Transfers and Microoperations Serial Transfers Used for narrow transfer paths Example 1: Telephone or cable line Parallel-to-Serial conversion at source Serial-to-Parallel conversion at destination Example 2: Initialization and Capture of the contents of many flip-flops for test purposes Add shift function to all flip-flops and form large shift register Use shifting for simultaneous Initialization and Capture operations Serial microoperations Example 1: Addition Example 2: Error-Correction for CDs
Slide 31 Serial MicrooperationsBy using two shift registers for operands, a full adder, and a flip flop (for the carry), we can add two numbers serially, starting at the least significant bit. Serial addition is a low cost way to add large numbers of operands, since a tree of full adder cells can be made to any depth, and each new level doubles the number of operands. Other operations can be performed serially as well, such as parity generation/checking or more complex error-checking codes. Serial Microoperations
Slide 32 Serial AdderThe circuit shown uses two shift registers for operands A(3:0) and B(3:0). A full adder, and one more flip flop (for the carry) is used to compute the sum. The result is stored in the A register and the final carry in the flip-flop With the operands and the result in shift registers, a tree of full adders can be used to add a large number of operands. Used as a common digital signal processing technique. A3 A2 A1 A0 B3 B2 B1 B0 A B Cin Sum Cout D Q CP FA Load/Right Shift Registers Serial In Serial In Parallel Load Parallel Load (Clock and Load/Shift Control not shown) Serial Adder
Slide 33 SummarySummary Microoperations on single register Counters Register cell design Multiplexer and bus-based transfers for multiple registers Serial transfers and microoperations
Table of ContentsThe object immediately following this sentence is the media player.