eTEACH presentation accessible player instructionseTEACH presentation accessible player instructionsThis eTEACH player requires that you have Flash 8 or above installed. If you do not, download the player from Adobe.
The next major heading marks the start of the presentation. Each next lower level heading thereafter marks the beginning of a slide. An audio control button that plays the audio track for the slide follows the contents and notes for each slide in the presentation. Pressing this button after the audio playback toggles pausing and resuming the playback. Before moving off the play audio button, complete listening to the audio track for the slide or pause the audio. Control + Shift + L increases volume. Control + Shift + Q decreases volume.
There is a table of contents for the presentation following the presentation. The table of contents can be used to access sections of the presentation in random order. Type Control + Shift + C to go to the table of contents.
When links to external resources are present in the presentation, a list of these resource links follows the table of contents. When following a link to a resource, you should remember which slide you were on. When you return to the main page, your screen-reader may not return you to that slide. You can use the table of contents or just click through the headings to return to the correct slide.
This presentation contains resources. Click here to proceed immediately to the resource list. A link to resources follows each slide.
If the presentation contains one or more quizzes, a button to take you to each quiz follows the slide at which the quiz is to occur. Each question in the quiz begins with a level three heading. The answer choices will be presented in a list. If your instructor has supplied a hint for the questions, it will follow the answers and is formatted as an anchor. The correct answer to the question follows the list of answers and the hint (if included). The correct answer is also formatted as an anchor.
Chapter 2 - Part 1 - PPT - Mano & Kime - 2nd EdSlide 1 Lecture 20 Analyzing Sequential LogicLecture 20 Analyzing Sequential Logic
Slide 2 OverviewOverview Finite State Machine Model State Tables State Diagrams Moore and Mealy Models Circuit and System Level Timing
Slide 3 Finite State Machine ModelFinite State Machine Model General Model Current State at time (t) is stored in an array of flip-flops. Next State at time (t+1) is a Boolean function of State and Inputs. Outputs at time (t) are a Boolean function of State (t) and (sometimes) Inputs (t). Combina-tional Logic Inputs State Next State Outputs Storage Elements CLK
Slide 4 Example 1 (from Fig. 6-17)Example 1 (from Fig. 6-17) Input: x(t) Output: y(t) State: (A(t), B(t)) What is the Output Function? What is the Next State Function? A C D Q Q C D Q Q y x A B CP
Slide 5 Example 1 (continued)Example 1 (continued) Where in time are inputs, outputs and states defined? 0 0 0 0 1 1 1 0
Slide 6 Example 1: State TableExample 1: State Table The state table can be filled in using the next state and output equations: Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t) 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0
Slide 7 Example 1: Alternate State TableExample 1: Alternate State Table 2-dimensional table that matches well to a K-map. Present state rows and input columns in Gray code order. A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) =A (t)x(t) y(t) =x (t)(B(t) + A(t)) Present State Next State x(t)=0 x(t)=1 Output x(t)=0 x(t)=1 A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t) 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0
Slide 8 State DiagramsState Diagrams Graphical specification Nodes states Edges transitions Depend on inputs Outputs Based on state Based on state and input A B 0 0 0 1 1 1 1 0 x=0/y=1 x=1/y=0 x=1/y=0 x=1/y=0 x=0/y=1 x=0/y=1 x=1/y=0 x=0/y=0
Type: Mealy
Slide 9 Moore and Mealy ModelsMoore and Mealy Models Finite State Machines (FSMs) have two formal models: In contemporary design, models are sometimes mixed Moore and Mealy Moore Model Named after E.F. Moore. Outputs are a function ONLY of states Usually specified on the states. Mealy Model Named after G. Mealy Outputs are a function of inputs AND states Usually specified on the state transition arcs.
Slide 10 Moore and Mealy Example DiagramsMoore and Mealy Example Diagrams Mealy Model State Diagram maps inputs and state to outputs Moore Model State Diagram maps states to outputs 0 1 x=1/y=1 x=1/y=0 x=0/y=0 x=0/y=0 1/0 2/1 x=1 x=1 x=0 x=0 x=1 x=0 0/0
Slide 11 Moore and Mealy Example TablesMoore and Mealy Example Tables Mealy Model state table maps inputs and state to outputs Moore Model state table maps state to outputs Present State Next State x=0 x=1 Output 0 0 1 0 1 0 2 0 2 0 2 1 Present State Next State x=0 x=1 Output x=0 x=1 0 0 1 0 0 1 0 1 0 1
Slide 12 Sequential Circuit Analysis ExampleSequential Circuit Analysis Example Logic Diagram: Clock Reset D Q C Q R D Q C Q R D Q C Q R A B C Z
Slide 13 Example 2: Flip-Flop Input EquationsExample 2: Flip-Flop Input Equations Variables Inputs: None Outputs: Z State Variables: A, B, C Initialization: Reset to (0,0,0) Equations:
A(t+1) = BC B(t+1) = B C + BC C(t+1) = A C Z = A
Slide 14 Example 2: State TableExample 2: State Table X = X(t+1)
A B C : 0 0 1, 0 1 0, 0 1 1, 1 0 0, 0 0 0, 0 1 0, 0 1 0, 1 0 0 Z: 0 0 0 0 1 1 1 1
Slide 15 Example 2: State DiagramWhich states are used? What is the function of the circuit? 000 011 010 001 100 101 110 111 Reset ABC Example 2: State Diagram
Only states reachable from the reset state 000 are used: 000, 001, 010, 011, and 100. The circuit produces a 1 on Z after four clock periods and every five clock periods thereafter: 000 -> 001 -> 010 -> 011 -> 100 -> 000 -> 001 -> 010 -> 011 -> 100 … 1 1
Slide 16 Circuit and System Level TimingConsider a system comprised of ranks of flip-flops connected by logic: If the clock period is too short, some data changes will not propagate through the circuit to flip-flop inputs before the setup time interval begins Circuit and System Level Timing C D Q Q' C D Q Q' C D Q Q' C D Q Q' C D Q Q' C D Q Q' C D Q Q' C D Q Q' C D Q Q' C D Q Q' CLOCK CLOCK
Slide 17 Circuit and System Level Timing (continued)Timing components along a path from flip-flop to flip-flop Circuit and System Level Timing (continued) (a) Edge-triggered (positive edge) t p t pd,FF t pd,COMB t slack t s C (b) Pulse-triggered (negative pulse) t p t pd,FF t pd,COMB t slack t s C
Slide 18 Circuit and System Level Timing (continued)New Timing Components tp - clock period - The interval between occurrences of a specific clock edge in a periodic clock tpd,COMB - total delay of combinational logic along the path from flip-flop output to flip-flop input tslack - extra time in the clock period in addition to the sum of the delays and setup time on a path Can be either positive or negative Must be greater than or equal to zero on all paths for correct operation Circuit and System Level Timing (continued)
Slide 19 Circuit and System Level Timing (continued)Timing Equations tp = tslack + (tpd,FF + tpd,COMB + ts) For tslack greater than or equal to zero, tp ≥ max (tpd,FF + tpd,COMB + ts) for all paths from flip-flop output to flip-flop input Can be calculated more precisely by using tPHL and tPLH values instead of tpd values, but requires consideration of inversions on paths Circuit and System Level Timing (continued)
Slide 20 Calculation of Allowable tpd,COMBCalculation of Allowable tpd,COMB Compare the allowable combinational delay for a specific circuit: a) Using edge-triggered flip-flops b) Using master-slave flip-flops Parameters tpd,FF(max) = 1.0 ns ts(max) = 0.3 ns for edge-triggered flip-flops ts = twH = 1.0 ns for master-slave flip-flops Clock frequency = 250 MHz
Slide 21 Calculation of Allowable tpd,COMB (continued)Calculation of Allowable tpd,COMB (continued) Calculations: tp = 1/clock frequency = 4.0 ns Edge-triggered: 4.0 ≥ 1.0 + tpd,COMB + 0.3 → tpd,COMB ≤ 2.7 ns Master-slave: 4.0 ≥ 1.0 + tpd,COMB + 1.0 → tpd,COMB ≤ 2.0 ns Comparison: Assume average gate tpd = 0.3 ns Edge-triggered: Approximately 9 gates allowed on a path Master-slave: Approximately 6 to 7 gates allowed on a path
Slide 22 SummarySummary Finite State Machine Model State Tables State Diagrams Moore and Mealy Models Circuit and System Level Timing
Table of ContentsThe object immediately following this sentence is the media player.