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Chapter 2 - Part 1 - PPT - Mano & Kime - 2nd EdSlide 1 OverviewOverview Iterative combinational circuits Binary adders Half and full adders Ripple carry and carry lookahead adders Unsigned Binary subtraction Complement Radix Complement Diminished Radix Complement Subtraction Using Complements
Slide 2 Iterative Combinational CircuitsIterative Combinational Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block for subfunction and repeat to obtain functional block for overall function Cell - subfunction block Iterative array - a array of interconnected cells An iterative array can be in a single dimension (1D) or multiple dimensions
Slide 3 Block Diagram of a 1D Iterative ArrayAdobe Systems Block Diagram of a 1D Iterative Array Example: n = 32 Number of inputs = ? Truth table rows = ? Equations with up to ? input variables Equations with huge number of terms Design impractical! Iterative array takes advantage of the regularity to make design feasible
Number of Inputs = 66 Truth Table Rows = 266 Equations with up to 66 variables
Slide 4 Functional Blocks: AdditionFunctional Blocks: Addition Binary addition used frequently Addition Development: Half-Adder (HA), a 2-input bit-wise addition functional block, Full-Adder (FA), a 3-input bit-wise addition functional block, Ripple Carry Adder, an iterative array to perform binary addition, and Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance.
Slide 5 Functional Block: Half-AdderFunctional Block: Half-Adder A 2-input, 1-bit width binary adder that performs the following computations: A half adder adds two bits to produce a two-bit sum The sum is expressed as a sum bit , S and a carry bit, C The half adder can be specified as a truth table for S and C X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 0 1 0 1 1 0 X Y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0
Slide 6 Implementations: Half-AdderImplementations: Half-Adder The most common half adder implementation is: (e) Y X C Y X S × = Å = X Y C S
Slide 7 Functional Block: Full-AdderFunctional Block: Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. For a carry-in (Z) of 0, it is the same as the half-adder: For a carry- in (Z) of 1: Z 0 0 0 0 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 0 1 0 1 1 0 Z 1 1 1 1 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 1 1 0 1 0 1 1
Slide 8 Logic Optimization: Full-AdderLogic Optimization: Full-Adder Full-Adder Truth Table: Full-Adder K-Map: X Y Z C S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 X Y Z 0 1 3 2 4 5 7 6 1 1 1 1 S X Y Z 0 1 3 2 4 5 7 6 1 1 1 1 C
Slide 9 Equations: Full-AdderEquations: Full-Adder From the K-Map, we get: The S function is the three-bit XOR function (Odd Function): The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if the sum is 1 and a carry-in (Z) occurs. Thus C can be re-written as: The term X·Y is carry generate. The term XY is carry propagate. Can also be implemented as (X+Y) Z Y Z X Y X C Z Y X Z Y X Z Y X Z Y X S + + = + + + = Z Y X S Å Å = Z ) Y X ( Y X C Å + =
Slide 10 Implementation: Full AdderImplementation: Full Adder Full Adder Schematic Here X, Y, and Z, and C (from the previous pages) are A, B, Ci and Co, respectively. Also, G = generate and P = propagate. Note: This is really a combination of a 3-bit odd function (for S)) and Carry logic (for Co): (G = Generate) OR (P =Propagate AND Ci = Carry In) Co = G + P · Ci Ai Bi Ci Ci+1 Gi Pi Si
Slide 11 Binary AddersBinary Adders To add multiple operands, we bundle logical signals together into vectors and use functional blocks that operate on the vectors Example: 4-bit ripple carry adder: Adds input vectors A(3:0) and B(3:0) to get a sum vector S(3:0) Note: carry out of cell i becomes carry in of cell i + 1 Description Subscript 3 2 1 0 Name Carry In 0 1 1 0 Ci Augend 1 0 1 1 Ai Addend 0 0 1 1 Bi Sum 1 1 1 0 Si Carry out 0 0 1 1 Ci+1
Slide 12 4-bit Ripple-Carry Binary Adder4-bit Ripple-Carry Binary Adder A four-bit Ripple Carry Adder made from four 1-bit Full Adders: Adobe Systems
Slide 13 Carry Propagation & DelayCarry Propagation & Delay Propagation delay: Carry must ripple from LSB to MSB. The gate-level propagation path for a 4-bit ripple carry adder of the last example: Too slow for many bits (e.g. 32 or 64) A3 B3 S3 B2 S2 B1 S1 S0 B0 A2 A1 A0 C4 C3 C2 C1 C0
Slide 14 Carry LookaheadCarry Lookahead Given Stage i from a Full Adder, we know that there will be a carry generated when Ai = Bi = "1", whether or not there is a carry-in. Alternately, there will be a carry propagated if the half-sum is "1" and a carry-in, Ci occurs. These two signal conditions are called generate, denoted as Gi, and propagate, denoted as Pi respectively and are identified in the circuit: Ai Bi Ci Ci+1 Gi Pi Si
Slide 15 Carry Lookahead (continued)Carry Lookahead (continued) In the ripple carry adder: Gi, Pi, and Si are local to each cell of the adder Ci is also local each cell In the carry lookahead adder, in order to reduce the length of the carry chain, Ci is changed to a more global function spanning multiple cells Defining the equations for the Full Adder in term of the Pi and Gi: i i i i i i B A G B A P = Å = i i i 1 i i i i C P G C C P S + = Å = +
Slide 16 Carry Lookahead DevelopmentCarry Lookahead Development Flatten equations for carry using Gi and Pi terms for less significant bits Beginning at the cell 0 with carry in C0: C1 = G0 + P0 C0 C4 = G3 + P3 C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0 C0 C2 = G1 + P1 C1 = G1 + P1(G0 + P0 C0) = G1 + P1G0 + P1P0 C0 C3 = G2 + P2 C2 = G2 + P2(G1 + P1G0 + P1P0 C0) = G2 + P2G1 + P2P1G0 + P2P1P0 C0
Slide 17 Group Carry Lookahead LogicGroup Carry Lookahead Logic Directly generating carry for 4 bits results in Fan-in of 5 for AND gate and fan-in of 5 for OR gate Beyond 4 bits is not feasible due to increased fan-in Use hierarchy instead! Consider group generate (G0-3) and group propagate (P0-3) functions: Using these two equations: Thus, it is possible to have four 4-bit adders use one of the same carry lookahead circuit to speed up 16-bit addition 0 1 2 3 3 0 0 0 1 2 3 1 2 3 2 3 3 3 0 P P P P P G P P P P G P P G P G G = + + + = - - 0 3 0 3 0 4 C P G C - - + =
Slide 18 Carry Lookahead ExampleCarry Lookahead Example Specifications: 16-bit CLA Delays: NOT = 1 XOR = 3 AND-OR = 2 Longest Delays: Ripple carry adder = 3 + 15 ´ 2 + 3 = 36 CLA = 3 + 3 ´ 2 + 3 = 12 Delay is proportional to log2(bits) CLA CLA CLA CLA CLA 3 3 2 2 2
Slide 19 Unsigned SubtractionUnsigned Subtraction Algorithm: Subtract N from M If no end borrow occurs, then M ³ N, and the result is a non-negative number and correct. If an end borrow occurs, then N > M and we really have M - N + 2n due to the final borrow Correct by subtracting from 2n, and appending minus sign Examples: 0 1 1001 0100 - 0111 - 0111 0010 1101 10000 - 1101 (-) 0011
Slide 20 Unsigned Subtraction (continued)Unsigned Subtraction (continued) The subtraction, 2n - N, is taking the 2 s complement of N To do both unsigned addition and unsigned subtraction requires: Quite complex! Goal: Shared simpler logic for both addition and subtraction Introduce complements as an approach Adobe Systems
Slide 21 ComplementsComplements Two complements: Diminished Radix Complement of N (r - 1) s complement for radix r 1 s complement for radix 2 Defined as (rn - 1) - N Radix Complement r s complement for radix r 2 s complement in binary Defined as rn - N Subtraction is done by adding the complement of the right-hand side If result is negative, take complement and add -
Slide 22 Binary 1's ComplementBinary 1's Complement For r = 2, N = 011100112, n = 8 (8 digits): (rn 1) = 256 -1 = 25510 or 111111112 The 1's complement of 011100112 is then: 11111111 01110011 10001100 Since the 2n 1 factor consists of all 1's and since 1 0 = 1 and 1 1 = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT).
Slide 23 Binary 2's ComplementBinary 2's Complement For r = 2, N = 011100112, n = 8 (8 digits), we have: (rn ) = 25610 or 1000000002 The 2's complement of 01110011 is then: 100000000 01110011 10001101 Note the result is the 1's complement plus 1, a fact that can be used in designing hardware
Slide 24 Alternate 2 s Complement MethodAlternate 2 s Complement Method Given: an n-bit binary number, beginning at the least significant bit and proceeding upward: Copy all least significant 0 s Copy the first 1 Complement all bits thereafter. 2 s Complement Example: 10010100 Copy underlined bits: 100 and complement bits to the left: 01101100
Slide 25 Subtraction with 2 s ComplementSubtraction with 2 s Complement For n-digit, unsigned numbers M and N, find M N in base 2: Add the 2's complement of N to M: M + (2n N) = M N + 2n = 2n (N M) If M N, the sum produces end carry 2n which is discarded; from above, M - N remains. If M < N, the sum does not produce an end carry and, from above, is equal to 2n ( N M ), the 2's complement of ( N M ). To obtain the result (N M) , take the 2's complement of the sum and place a to its left.
Slide 26 Unsigned 2 s Complement Subtraction Example 1Unsigned 2 s Complement Subtraction Example 1 Find 010101002 010000112 01010100 01010100 01000011 + 10111101 00010001 The carry of 1 indicates that no correction of the result is required. 1 2 s comp
Slide 27 Unsigned 2 s Complement Subtraction Example 2Unsigned 2 s Complement Subtraction Example 2 Find 010000112 010101002 01000011 01000011 01010100 + 10101100 11101111 00010001 The carry of 0 indicates that a correction of the result is required. Result = (00010001) 0 2 s comp 2 s comp
Slide 28 SummarySummary Iterative combinational circuits Binary adders Half and full adders Ripple carry and carry lookahead adders Unsigned Binary subtraction Complement Radix Complement Diminished Radix Complement Subtraction Using Complements
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