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ECE352_10

Slide 1 Lecture 10 Other Gate Types

Lecture 10 Other Gate Types

Slide 2 Outline

Outline Other Gate Types Buffer NAND NOR XOR & XNOR High-Impedance Outputs 3-State Buffers Transmission Gates Other complex gates

Slide 3 Other Gate Types

Other Gate Types Why? Implementation feasibility and low cost Power in implementing Boolean functions Convenient conceptual representation Gate classifications Primitive gate - a gate that can be described using a single primitive operation type (AND or OR) plus an optional inversion(s). Complex gate - a gate that requires more than one primitive operation type for its description Primitive gates will be covered first

Slide 4 Buffer

Buffer A buffer is a gate with the function F = X: In terms of Boolean function, a buffer is the same as a connection! So why use it? A buffer is an electronic amplifier used to improve circuit voltage levels and increase the speed of circuit operation. X F

Slide 5 NAND Gate

NAND Gate The basic NAND gate has the following symbol, illustrated for three inputs: AND-Invert (NAND) NAND represents NOT AND, i. e., the AND function with a NOT applied. The symbol shown is an AND-Invert. The small circle ( bubble ) represents the invert function. X Y Z Z Y X ) Z , Y , X ( F × × =

Slide 6 NAND Gates (continued)

NAND Gates (continued) Applying DeMorgan's Law gives Invert-OR (NAND) This NAND symbol is called Invert-OR, since inputs are inverted and then ORed together. AND-Invert and Invert-OR both represent the NAND gate. Having both makes visualization of circuit function easier. A NAND gate with one input degenerates to an inverter. X Y Z Z Y X ) Z , Y , X ( F + + = Z Y X ) Z , Y , X ( F × × = Z Y X + + =

Slide 7 NAND Gates (continued)

NAND Gates (continued) The NAND gate is the natural implementation for the simplest and fastest electronic circuits Universal gate - a gate type that can implement any Boolean function. The NAND gate is a universal gate as shown in Figure 2-30 of the text. NAND usually does not have a operation symbol defined since the NAND operation is not associative, and we have difficulty dealing with non-associative mathematics!

Slide 8 NOR Gate

NOR Gate The basic NOR gate has the following symbol, illustrated for three inputs: OR-Invert (NOR) NOR represents NOT - OR, i. e., the OR function with a NOT applied. The symbol shown is an OR-Invert. The small circle ( bubble ) represents the invert function. X Y Z Z Y X ) Z , Y , X ( F + + =

Slide 9 NOR Gate (continued)

NOR Gate (continued) Applying DeMorgan's Law gives Invert-AND (NOR) This NOR symbol is called Invert-AND, since inputs are inverted and then ANDed together. OR-Invert and Invert-AND both represent the NOR gate. Having both makes visualization of circuit function easier. A NOR gate with one input degenerates to an inverter. X Y Z Z Y X ) Z , Y , X ( F = Z Y X ) Z , Y , X ( F + + = Z Y X =

Slide 10 NOR Gate (continued)

NOR Gate (continued) The NOR gate is another natural implementation for the simplest and fastest electronic circuits The NOR gate is a universal gate NOR usually does not have a defined operation symbol since the NOR operation is not associative, and we have difficulty dealing with non-associative mathematics!

Slide 11 Exclusive OR/ Exclusive NOR

Exclusive OR/ Exclusive NOR The eXclusive OR (XOR) function is an important Boolean function used extensively in logic circuits. The XOR function may be; implemented directly as an electronic circuit (truly a gate) or implemented by interconnecting other gate types (used as a convenient representation) The eXclusive NOR function is the complement of the XOR function By our definition, XOR and XNOR gates are complex gates.

Slide 12 Exclusive OR/ Exclusive NOR

Exclusive OR/ Exclusive NOR Uses for the XOR and XNORs gate include: Adders/subtractors/multipliers Counters/incrementers/decrementers Parity generators/checkers Definitions The XOR function is: The eXclusive NOR (XNOR) function, otherwise known as equivalence is: Strictly speaking, XOR and XNOR gates do not exist for more that two inputs. Instead, they are replaced by odd and even functions. Y X Y X Y X + = Å Y X Y X Y X + = Å

Slide 13 Truth Tables for XOR/XNOR

Truth Tables for XOR/XNOR Operator Rules: XOR XNOR The XOR function means: X OR Y, but NOT BOTH Why is the XNOR function also known as the equivalence function, denoted by the operator ? X Y X Å Y 0 0 0 0 1 1 1 0 1 1 1 0 X Y 0 0 1 0 1 0 1 0 0 1 1 1 or X º Y (X Å Y)

Slide notes

Because it is defined as X Y + X Y that equals 1 if and only if X = Y implying X is equivalent to Y.

Slide 14 XOR/XNOR (Continued)

XOR/XNOR (Continued) The XOR function can be extended to 3 or more variables. For more than 2 variables, it is called an odd function or modulo 2 sum (Mod 2 sum), not an XOR: The complement of the odd function is the even function. The XOR identities: = = X 1 X X 0 X Å Å 1 X X 0 X X = Å = Å X Y Y X Å = Å Z Y X ) Z Y ( X Z ) Y X ( Å Å = Å Å = Å Å + + + = Å Å Z Y X Z Y X Z Y X Z Y X Z Y X

Slide 15 Symbols For XOR and XNOR

Symbols For XOR and XNOR XOR symbol: XNOR symbol: Symbols exist only for two inputs

Slide 16 XOR Implementations

XOR Implementations The simple SOP implementation uses the following structure: A NAND only implementation is: X Y X Y X Y X Y

Slide 17 Odd and Even Functions

Odd and Even Functions The odd and even functions on a K-map form checkerboard patterns. The 1s of an odd function correspond to minterms having an index with an odd number of 1s. The 1s of an even function correspond to minterms having an index with an even number of 1s. Implementation of odd and even functions for greater than 4 variables as a two-level circuit is difficult, so we use trees made up of : 2-input XOR or XNORs 3- or 4-input odd or even functions

Slide 18 Example: Odd Function Implementation

Example: Odd Function Implementation Design a 3-input odd function F = X Y Z with 2-input XOR gates Factoring, F = (X Y) Z The circuit: + + + + X Y Z F

Slide 19 Example: Even Function Implementation

Example: Even Function Implementation Design a 4-input even function F = W X Y Z with 2-input XOR and XNOR gates Factoring, F = (W X) (Y Z) The circuit: + + + W X Y F Z + + +

Slide 20 Parity Generators and Checkers

Parity Generators and Checkers In Chapter 1, a parity bit added to n-bit code to produce an n + 1 bit code: Add odd parity bit to generate code words with even parity (1001) Add even parity bit to generate code words with odd parity (0001) Use odd parity circuit to check code words with even parity Use even parity circuit to check code words with odd parity Example: n = 3. Generate even parity code words of length 4 with odd parity generator: Check even parity code words of length 4 with odd parity checker: Operation: (X,Y,Z) = (0,0,1) gives (X,Y,Z,P) = (0,0,1,1) and E = 0. If Y changes from 0 to 1 between generator and checker, then E = 1 indicates an error. X Y Z P X Y Z E P

Slide 21 Hi-Impedance Outputs

Hi-Impedance Outputs Logic gates introduced thus far have 1 and 0 output values, cannot have their outputs connected together, and transmit signals on connections in only one direction. Three-state logic adds a third logic value, Hi-Impedance (Hi-Z), giving three states: 0, 1, and Hi-Z on the outputs. The presence of a Hi-Z state makes a gate output as described above behave quite differently: 1 and 0 become 1, 0, and Hi-Z cannot becomes can, and only one becomes two

Slide 22 Hi-Impedance Outputs (continued)

Hi-Impedance Outputs (continued) What is a Hi-Z value? The Hi-Z value behaves as an open circuit This means that, looking back into the circuit, the output appears to be disconnected. It is as if a switch between the internal circuitry and the output has been opened. Hi-Z may appear on the output of any gate, but we restrict gates to: a 3-state buffer, or a transmission gate, each of which has one data input and one control input. Hi-Z

Slide 23 The 3-State Buffer

The 3-State Buffer For the symbol and truth table, IN is the data input, and EN, the control input. For EN = 0, regardless of the value on IN (denoted by X), the output value is Hi-Z. For EN = 1, the output value follows the input value. Variations: Data input, IN, can be inverted Control input, EN, can be inverted by addition of bubbles to signals. IN EN OUT EN IN OUT 0 X Hi-Z 1 0 0 1 1 1 Symbol Truth Table

Slide 24 Resolving 3-State Values on a Connection

Resolving 3-State Values on a Connection Connection of two 3-state buffer outputs, B1 and B0, to a wire, OUT Assume: Buffer data inputs can take on any combination of values 0 and 1 Resulting Rule: At least one buffer output value must be Hi-Z. For n 3-state buffers connected to a wire, (n-1) buffers must be Hi-Z? 2n+1 valid buffer output combinations IN0 IN1 EN0 EN1 OUT B1 B0

Slide notes

One buffer output Hi-Z? Because any data combinations including (0,1) and (1,0) can occur. If one of these combinations occurs, and no buffers are Hi-Z, then high currents can occur, destroying or damaging the circuit. Valid buffer output combinations? 5 Rule for n 3-state buffers? n-1 buffer outputs must be Hi-Z. Valid buffer output combinations? Each of the n-buffers can have a 0 or 1 output with all others at Hi-Z. Also all buffers can be Hi-Z. So there are 2n + 1 valid combinations.

Slide 25 3-State Logic Circuit

3-State Logic Circuit Data Selection Function: If s = 0, OL = IN0, else OL = IN1 Performing data selection with 3-state buffers: Since EN0 = S and EN1 = S, one of the two buffer outputs is always Hi-Z plus the last row of the table never occurs. IN0 IN1 EN0 EN1 S OL

Slide 26 Transmission Gates

Transmission Gates The transmission gate is one of the designs for an electronic switch for connecting and disconnecting two points in a circuit: (a) X Y TG C C (c) C = 0 and C = 1 X Y = Hi-Z (b) X Y = X C = 1 and C = 0 (d) X Y C TG

Slide 27 Transmission Gates (continued)

Transmission Gates (continued) In many cases, X can be regarded as a data input and Y as an output. C and C, with complementary values applied, is a control input. With these definitions, the transmission gate, provides a 3-state output: C = 1, Y = X (X = 0 or 1) C = 0, Y = Hi-Z Care must be taken when using the TG in design, however, since X and Y as input and output are interchangeable, and signals can pass in both directions.

Slide 28 Circuit Example Using TG

Adobe Systems Exclusive OR F = A C The basis for the function implementation is TG-controlled paths to the output Circuit Example Using TG +

Slide 29 More Complex Gates

More Complex Gates The remaining complex gates are SOP or POS structures with and without an output inverter. The names are derived using: A - AND O - OR I - Inverter Numbers of inputs on first-level gates or directly to second-level gates

Slide 30 More Complex Gates (continued)

More Complex Gates (continued) Example: AOI - AND-OR-Invert consists of a single gate with AND functions driving an OR function which is inverted. Example: 2-2-1 AO has two 2-input ANDS driving an OR with one additional OR input These gate types are used because: the number of transistors needed is fewer than required by connecting together primitive gates potentially, the circuit delay is smaller, increasing the circuit operating speed

Slide 31 Summary

Summary Other Gate Types Buffer NAND NOR XOR/XNOR High-Impedance Outputs 3-State Buffers Transmission Gates Other complex gates

End of slides

Table of Contents

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