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Chapter 2 - Part 1 - PPT - Mano & Kime - 2nd EdSlide 1 Lecture 18 Introduction to Sequential LogicLecture 18 Introduction to Sequential Logic
Slide 2 OverviewOverview Introduction to sequential circuits Discrete event simulation Types of sequential circuits Latch-based storage S/R latch Clocked S/R latch D latch
Slide 3 Introduction to Sequential CircuitsIntroduction to Sequential Circuits A Sequential circuit contains: Storage elements: Latches or Flip-Flops Combinational Logic: Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. Combina-tional Logic Storage Elements Inputs Outputs State Next State
Slide 4 Introduction to Sequential CircuitsCombinatorial Logic Next state function Next State = f(Inputs, State) Output function (Mealy) Outputs = g(Inputs, State) Output function (Moore) Outputs = h(State) Output function type depends on specification and affects the design significantly Combina-tional Logic Storage Elements Inputs Outputs State Next State Introduction to Sequential Circuits
Slide 5 Types of Sequential CircuitsTypes of Sequential Circuits Depends on the times at which: storage observes inputs, and storage changes state Synchronous Inputs sampled at discrete instances of time Storage changes state at clock pulses Asynchronous Inputs sampled continuously State changes at any time If clock just regarded as another input, all circuits are asynchronous! Synchronous is an abstraction Makes design, analysis reasonable and tractable
Slide 6 Discrete Event SimulationDiscrete Event Simulation In order to understand the time behavior of a sequential circuit we use discrete event simulation. Rules: Gates modeled by an ideal (instantaneous) function and a fixed gate delay Any change in input values is evaluated to see if it causes a change in output value Changes in output values are scheduled for the fixed gate delay after the input change At the time for a scheduled output change, the output value is changed along with any inputs it drives
Slide 7 Simulated NAND GateSimulated NAND Gate Example: A 2-Input NAND gate with a 0.5 ns. delay: Assume A and B have been 1 for a long time At time t=0, A changes to a 0 at t= 0.8 ns, back to 1. F A B DELAY 0.5 ns. F(Instantaneous) t (ns) A B F(I) F Comment 1 1 0 0 A=B=1 for a long time 0 1 Þ 0 1 1 Ü 0 0 F(I) changes to 1 0.5 0 1 1 1 Ü 0 F changes to 1 after a 0.5 ns delay 0.8 1 Ü 0 1 1 Þ 0 1 F(Instantaneous) changes to 0 0.13 1 1 0 1 Þ 0 F changes to 0 after a 0.5 ns delay
Slide 8 Gate Delay ModelsGate Delay Models Annotate gates with delays 0.2 0.5 0.4
Slide 9 Circuit Delay ModelConsider a simple 2-input multiplexer: With function: Y = A for S = 1 Y = B for S = 0 Glitch is due to delay of inverter A 0.4 0.5 0.4 S B Y 0.2 Circuit Delay Model A S B Y S
Slide 10 Storing StateStoring State What if A con- nected to Y? Circuit becomes: With function: Y = B for S = 1, and Y(t) dependent on Y(t 0.9) for S = 0 The simple combinational circuit has now become a sequential circuit because its output is a function of a time sequence of input signals! B S Y S S B Y 0.5 0.4 0.2 0.4 Y is stored value in shaded area
Slide 11 Storing State (Continued)Storing State (Continued) Simulation example as input signals change with time. Changes occur every 100 ns, so that the tenths of ns delays are negligible. Y represent the state of the circuit, not just an output. B S Y Comment 1 0 0 Y remembers 0 1 1 1 Y = B when S = 1 1 0 1 Now Y remembers B = 1 for S = 0 0 0 1 No change in Y when B changes 0 1 0 Y = B when S = 1 0 0 0 Y remembers B = 0 for S = 0 1 0 0 No change in Y when B changes Time
Note that the glitch is still present. An actual storage circuit would be designed to eliminate this by addition of term BY.
Slide 12 Basic (NAND) S R LatchBasic (NAND) S R Latch Cross-Coupling two NAND gates gives the S -R Latch: Which has the time sequence behavior: S = 0, R = 0 is forbidden as input pattern Q S (set) R (reset) Q R S Q Q Comment 1 1 ? ? Stored state unknown 1 0 1 0 Set Q to 1 1 1 1 0 Now Q remembers 1 0 1 0 1 Reset Q to 0 1 1 0 1 Now Q remembers 0 0 0 1 1 Both go high 1 1 ? ? Unstable! Time
Slide 13 Basic (NOR) S R LatchBasic (NOR) S R Latch Cross-coupling two NOR gates gives the S R Latch: Which has the time sequence behavior: S (set) R (reset) Q Q R S Q Q Comment 0 0 ? ? Stored state unknown 0 1 1 0 Set Q to 1 0 0 1 0 Now Q remembers 1 1 0 0 1 Reset Q to 0 0 0 0 1 Now Q remembers 0 1 1 0 0 Both go low 0 0 ? ? Unstable! Time
Slide 14 Storing State (Continued)Storing State (Continued) Simulation example as input signals change with time. Changes occur every 100 ns, so that the tenths of ns delays are negligible. Y represent the state of the circuit, not just an output. B S Y Comment 1 0 0 Y remembers 0 1 1 1 Y = B when S = 1 1 0 1 Now Y remembers B = 1 for S = 0 0 0 1 No change in Y when B changes 0 1 0 Y = B when S = 1 0 0 0 Y remembers B = 0 for S = 0 1 0 0 No change in Y when B changes Time
Note that the glitch is still present. An actual storage circuit would be designed to eliminate this by addition of term BY.
Slide 15 Basic (NOR) S R LatchBasic (NOR) S R Latch Cross-coupling two NOR gates gives the S R Latch: Which has the time sequence behavior: S (set) R (reset) Q Q R S Q Q Comment 0 0 ? ? Stored state unknown 0 1 1 0 Set Q to 1 0 0 1 0 Now Q remembers 1 1 0 0 1 Reset Q to 0 0 0 0 1 Now Q remembers 0 1 1 0 0 Both go low 0 0 ? ? Unstable! Time
Slide 16 Clocked S - R LatchClocked S - R Latch Adding two NAND gates to the basic S - R NAND latch gives the clocked S R latch: Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high. C means control or clock . S R Q C Q
Slide 17 Clocked S - R Latch (continued)Clocked S - R Latch (continued) S R Q Q C The Clocked S-R Latch can be described by a table: The table describes what happens after the clock [at time (t+1)] based on: current inputs (S,R) and current state Q(t).
Slide 18 D LatchD Latch Adding an inverter to the S-R Latch, gives the D Latch: Note that there are no indeterminate states! Q D Q(t+1) Comment 0 0 0 No change 0 1 1 Set Q 1 0 0 Clear Q 1 1 1 No Change C D Q Q D Q C Q
Slide 19 SummarySummary Introduction to sequential circuits Discrete event simulation Types of sequential circuits Latch-based storage S/R latch Clocked S/R latch D latch
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