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ECE352_15Slide 1 Lecture 15 Structured Implementation MethodsLecture 15 Structured Implementation Methods
Slide 2 OverviewOverview Implementing Combinational Functions Using: Decoders and OR gates Multiplexers (and inverter) ROMs PLAs PALs Lookup Tables
Slide 3 Combinational Function ImplementationCombinational Function Implementation Alternative implementation techniques: Decoders and OR gates Multiplexers (and inverter) ROMs PLAs PALs Lookup Tables Can be referred to as structured implementation methods since a specific underlying structure is assumed in each case
Slide 4 Decoder and OR GatesDecoder and OR Gates Implement m functions of n variables with: Sum-of-minterms expressions One n-to-2n-line decoder m OR gates, one for each output Procedure: Find the truth table for the functions or identify all minterms Connect corresponding decoder outputs to OR gate
Slide 5 Decoder and OR Gates ExampleDecoder and OR Gates Example Implement the following set of odd parity functions of (A7, A6, A5, A3) P1 = A7 A5 A3 P2 = A7 A6 A3 P4 = A7 A6 A5 Finding sum of minterms expressions P1 = Sm(1,2,5,6,8,11,12,15) P2 = Sm(1,3,4,6,8,10,13,15) P4 = Sm(2,3,4,5,8,9,14,15) Find circuit Is this a good idea? + + + + + + 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A7 A6 A5 A4 P1 P4 P2
No. The complexity is high. Much better to implement the functions with XOR gates. Also, the sharing of logic can cause 2 bits in error, which for this application (a Hamming encoder) is not detectable! Note that XOR gates should not be shared in the implementation as well.
Slide 6 Multiplexer Approach 1Multiplexer Approach 1 Implement m functions of n variables with: Sum-of-minterms expressions An m-wide 2n-to-1-line multiplexer Design: Find the truth table for the functions. In the order they appear in the truth table: Apply the function input variables to the multiplexer inputs Sn - 1, … , S0 Label the outputs of the multiplexer with the output variables Value-fix the information inputs to the multiplexer using the values from the truth table (for don t cares, apply either 0 or 1)
Slide 7 Example: Gray to Binary CodeExample: Gray to Binary Code Design a circuit to convert a 3-bit Gray code to a binary code The formulation gives the truth table on the right It is obvious from this table that X = C and the Y and Z are more complex Gray A B C Binary x y z 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1
Slide 8 Gray to Binary (continued)Gray to Binary (continued) Rearrange the table so that the input combinations are in counting order Functions y and z can be implemented using a dual 8-to-1-line multiplexer by: connecting A, B, and C to the multiplexer select inputs placing y and z on the two multiplexer outputs connecting their respective truth table values to the inputs
Slide 9 Gray to Binary (continued)Note that the multiplexer with fixed inputs is identical to a ROM with 3-bit addresses and 2-bit data! Gray to Binary (continued) D04 D05 D06 D07 S1 S0 A B S2 D03 D02 D01 D00 Out C D14 D15 D16 D17 S1 S0 A B S2 D13 D12 D11 D10 Out C 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Y Z 8-to-1 MUX 8-to-1 MUX
Slide 10 Multiplexer Approach 2Multiplexer Approach 2 Implement any m functions of n + 1 variables by using: An m-wide 2n-to-1-line multiplexer A single inverter Design: Find the truth table for the functions. Based on the values of the first n variables, separate the truth table rows into pairs For each pair and output, define a rudimentary function of the final variable (0, 1, X, ) Using the first n variables as the index, value-fix the information inputs to the multiplexer with the corresponding rudimentary functions Use the inverter to generate the rudimentary function X X
Slide 11 Example: Gray to Binary CodeExample: Gray to Binary Code Design a circuit to convert a 3-bit Gray code to a binary code The formulation gives the truth table on the right It is obvious from this table that X = C and the Y and Z are more complex Gray A B C Binary x y z 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1
Slide 12 Gray to Binary (continued)Gray to Binary (continued) Rearrange the table so that the input combinations are in counting order, pair rows, and find rudimentary functions F = C F = C F = C F = C F = C F = C F = C F = C
Slide 13 Gray to Binary (continued)Assign the variables and functions to the multiplexer inputs: Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1. This result is no longer ROM-like Extending, a function of more than n variables is decomposed into several sub-functions defined on a subset of the variables. The multiplexer then selects among these sub-functions. Gray to Binary (continued) S1 S0 A B D03 D02 D01 D00 Out Y 8-to-1 MUX C C C C D13 D12 D11 D10 Out Z 8-to-1 MUX S1 S0 A B C C C C C C
Slide 14 Read Only MemoryRead Only Memory Functions are implemented by storing the truth table Other representations such as equations more convenient Generation of programming information from equations usually done by software Text Example 4-10 Issue Two outputs are generated outside of the ROM In the implementation of the system, these two functions are hardwired and even if the ROM is reprogrammable or removable, cannot be corrected or updated
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Slide 15 Programmable Logic ArrayProgrammable Logic Array
Slide 16 Programmable Logic ArrayProgrammable Logic Array Limited number of product terms Often complement function contains fewer product terms PLAs typically support output inversion Literal count per product term is not limited For small circuits, K-maps can be used to visualize product term sharing and use of complements For larger circuits, software is used to do the optimization including use of complemented functions
Slide 17 Programmable Logic Array ExampleProgrammable Logic Array Example K-map specification How can this be implemented with four terms? Complete the programming table Outputs 1 2 3 4 F 2 1 1 1 AB AC BC Inputs 1 1 C 1 1 A 1 1 B PLA programming table (T) F 1 (F) Product term F 1 = A BC + A B C + A B C F 1 = AB + AC + BC + A B C 0 C 0 1 0 1 0 0 00 01 11 10 BC A 0 B 1 1 A 0 C 0 1 0 1 1 00 01 11 10 BC A 1 B 0 1 A F 2 = AB + AC + BC F 2 = AC + AB + B C 0 1 1 1 1
Slide 18 Programmable Logic Array ExampleProgrammable Logic Array Example X Fuse intact + Fuse blown 0 1 F 1 F 2 A B C C B A C B A 1 2 4 3 X X X X X X X X X X X X X X X X X X
Slide 19 Programmable Array LogicProgrammable Array Logic X X X X X X X X X X X X X X X X X X X AND gates inputs A C W Product term 1 2 3 4 5 6 7 8 9 10 11 12 A B C D W F1 F2 All fuses intact (always = 0) X Fuse intact X A B B C D D W A C W A B B C D D W 1 Fuse blown
Slide 20 Programmable Array LogicProgrammable Array Logic No sharing of AND gates Limited number of product terms (e.g. 3) Can daisy-chain multiple levels (factor)
Slide 21 Programmable Array Logic ExamplePr od uc t term AND Inputs Outputs A B C D W 1 2 3 W = C 4 5 6 F1 = X = A + B + W 7 8 9 10 11 12 A B C + ABC F2 = Y = AB + BC +AC B C A 1 0 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 Equations: F1 = A + B + C + ABC F2 = AB + BC + AC F1 must be factored since four terms Factor out last two terms as W A B B C C A Programmable Array Logic Example
Slide 22 Programmable Array Logic ExampleProgrammable Array Logic Example X X X X X X X X X X X X X X X X X X X AND gates inputs A C W Product term 1 2 3 4 5 6 7 8 9 10 11 12 A B C D W F1 F2 All fuses intact (always = 0) X Fuse intact X A B B C D D W A C W A B B C D D W 1 Fuse blown
Slide 23 Lookup TablesLookup Tables Lookup tables Field-Programmable Gate Arrays (FPGAs) Complex Programmable Logic Devices (CPLDs) Typically small Four inputs, one output, and 16 entries Possible to implement any 4-input function Design: How to optimally decompose a set of given functions into a set of 4-input two-level functions. We will illustrate this by a manual attempt
Slide 24 Lookup Table ExampleLookup Table Example Equations to be implemented: F1(A,B,C,D,E) = A D E + B D E + C D E F2(A,B,D,E,F) = A E D + B D E + F D E Extract 4-input function: F3(A,B,D,E) = A D E + B D E F1(C,D,E,F3) = F3 + C D E F2(D,E,F,F3) = F3 + F D E The cost of the solution is 3 lookup tables
Slide 25 SummarySummary Implementing Combinational Functions Using: Decoders and OR gates Multiplexers (and inverter) ROMs PLAs PALs Lookup Tables
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